1. Field of the Invention
The present invention generally relates to programmable logic devices, and more particularly, to a software redundancy method and module for use in the programming software used to program programmable logic devices and which provides improved interconnect efficiency on the programmable logic device.
2. Description of Related Art
A Programmable Logic Device (PLD) is a semiconductor integrated circuit that contains fixed logic circuitry that can be programmed to perform a host of logic functions. In the semiconductor industry, PLDs are becoming increasingly popular for a number of reasons. Due to the advances of chip manufacturing technology, application specific integrated circuits (ASICs) designs have become incredibly complex. This complexity not only adds to design costs, but also the duration of time needed to develop an application specific design. To compound this problem, product life cycles are shrinking rapidly. As a result, it is often not feasible for original equipment manufacturers (OEMs) to design and use ASICs. OEMs are therefore relying more and more on PLDs. The same advances in fabrication technology have also resulted in PLDs with improved density and speed performance. Sophisticated programming software enables complex logic functions to be rapidly developed for PLDs. Furthermore, logic designs generally can also be easily migrated from one generation of PLDs to the next, further reducing product development times. The closing of the price-performance gap with ASICs and reduced product development times makes the use of PLDs compelling for many OEMs.
The architecture of most commercially available PLDs contain a two-dimensional array of logic blocks. A series of row and column interconnects, typically of varying length and speed, provide signal and clock interconnects between blocks of logic on the PLD. The basic building blocks of logic are often referred to by such names as Logic Elements or Adaptive Logic Modules (ALMs) by the Altera Corporation, assignee of the present application, or Complex Logic Blocks (CLBs), as described by Xilinx Corporation. In the Altera architectures, the LEs or ALMs are organized into groups referred to as Logic Array Blocks or LABs. With the Xilinx architecture, multiple CLBs are organized into a slice. The LEs, ALMS and CLBs each typically include such elements as look up tables (LUTs), registers for generating registered logic outputs, adders and other circuitry to implement various logic and arithmetic functions. For the sake of simplicity, any block of logic containing multiple LEs, ALMs or CLBs, regardless if organized into a LAB or a slice, are hereafter generically referred to as LABs. In no way should the term LAB be construed as limiting to a particular PLD architecture and is intended to cover the blocks of logic as implemented on commercially offered devices such as those offered by Altera, Xilinx as described above, or any other vendor.
The interconnect of many commercially available PLDs includes at least two levels. A so called global interconnect provides the routing of signals between LABs. A second, lower level interconnect, provides the routing of signals within a given LAB. The global interconnect typically includes a plurality of horizontal and vertical channels or lines running the width and height of the chip respectively. Each channel is divided into buffered segments. The length of each segment is measured in terms of the number of LABs it spans. For example, if a vertical channel is buffered every fourth LAB, then the segment is designated as a V4 segment. Similarly, a horizontal segment that spans four LABs is designated as an H4 segment. The buffers are provided to boost the strength of a signal traversing the segments of a channel. A switching multiplexer is also typically associated with each buffer. The combination of the switching multiplexer and the buffer allow a line segment to be “stitched” or driven by the previous line segment in its own or some other channel. The combination also allows a line segment to be driven by an orthogonal line segment or an LE from an adjacent LAB.
Large programmable logic devices often have manufacturing defects. To increase yield, programmable redundancy can be applied to repair some of these manufacturing defects. This is typically done by adding one or more redundant “rows” per device. If a defect occurs in one of the rows, the defective row is disabled and all of the rows between the defective row and the redundant row are logically shifted over one row to physically bypass and logically remove the defective row from the device. This is accomplished by shifting the programming data for each row to the adjacent row.
With redundancy however, the vertical routing segments must configured to span a defective row in the event redundancy is implemented. With this vertical routing constraint, each “NV” long vertical routing segment, where N equals the number of LABs spanned by the segment between buffers, actually has to span a total of N+1 LABs. For example, a “V4” segment actually spans five LABs. The additional height or length is often referred to as a “redundancy tail” and is required to drive the N+1 LAB in the shifted row when redundancy is implemented.
Programming software is used to develop the logic designs that are to be implemented on PLD devices. The design flow of a typical programming software package generally includes design entry, synthesis, place and route, timing analysis, simulation and finally the configuration of the PLD device. A user will typically enter a logic design using a high level language such as Verilog or VHDL. Once the logic design has been entered, a gate level netlist is extracted from Verilog or VHDL. In the synthesis step, the netlist is broken down and implemented into the actual hardware resources available on the PLD device. The place and route module arranges the necessary hardware resource to implement the design on the device as efficiently as possible. Thereafter, the design is simulated and timing analysis is performed. Any modifications to the design to meet timing or performance specifications are typically identified and corrected at this stage. Once the design is finalized, the programming software next converts the output of the place and route module into a programming file. The programming contains the individual bits used to configure or program the hardware on the PLD to implement the intended logic design on the device.
The problem with the aforementioned redundancy scheme is the tails required to span the N+1 LAB for redundancy require a separate physical metal trace on the chip. The extra trace is therefore overhead that reduces the number of row and/or column channels that could otherwise be implemented within the device architecture. The interconnect efficiency on the PLD is therefore adversely effected by the use of redundancy on the device.
A software redundancy method and module for use in the programming software used to program programmable logic devices and which provides improved interconnect efficiency on the programmable logic device is therefore needed.